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asahi kasei [AK4356] m0072-e-01 1999/09 - 1 - general description the AK4356 is a high performance six channels dac corresponding to 96khz sampling mode of dvd. two channels of them can operate up to 192khz sampling fully correspond to dvd-audio standards. the AK4356 introduces the advanced multi-bit architecture for ds modulator. this new architecture achieves the wider dynamic range, while keeping much the same superior distortion characteristics as conventional single bit way. in the AK4356, the analog outputs are filtered in the analog domain by switched-capacitor filter (scf) with high tolerance to clock jitter. the analog outputs are full differential output, so the device is suitable for hi-end applications. features o 128x oversampling o sampling rate up to 192khz for 2 channels mode, 96khz for 6 channels mode o 24bit 8 times digital filter with slow roll-off option ripple: 0.005db, attenuation: 75db o thd+n: -94db o dr, s/n: 112db o high tolerance to clock jitter o low distortion differential output o channel independent digital de-emphasis for 32, 44.1 & 48khz sampling o channel independent zero detect pin o channel independent digital attenuator with soft-transition o soft mute o 3-wire serial interface for volume control o i/f format: msb justified, lsb justified, i2s o ttl level digital i/f o master clock normal speed: 256fs, 384fs, 512fs or 768fs double speed: 128fs, 192fs, 256fs or 384fs o power supply: 4.75 to 5.25v o 44pin lqfp package o ta: -40 to 85 c 192khz 24bit six-channel dac for dvd-audio AK4356
asahi kasei [AK4356] m0072-e-01 1999/09 - 2 - n block diagram scf dac datt dzfl1 lout1+ lout1- scf dac datt dzfr1 rout1+ rout1- scf dac datt dzfl2 lout2+ lout2- scf dac datt dzfr2 rout2+ rout2- scf dac datt dzfl3 lout3+ lout3- scf dac datt dzfr3 rout3+ rout3- audio i/f control register AK4356 mclk lrck bick mck o lrck bick xti xto controller cs cclk cdti lrck bick sdout1 sdout2 sdout3 ac3 sdti1 sdti2 sdti3
asahi kasei [AK4356] m0072-e-01 1999/09 - 3 - n ordering guide AK4356vq -40 ~ +85 c 44pin lqfp(0.8mm pitch) akd4356 evaluation board n pin layout lout1- rout 1+ 1 lout1+ 44 2 dzfl2 3 dzfr1 4 dzfl1 5 c ad0 6 c ad1 7 pdn 8 bick 9 mclk 10 dvdd 11 rout 1- 43 lout 2+ 42 lout 2- 41 rout 2+ 40 rout 2- 39 lout 3+ 38 lout 3- 37 rout 3+ 36 rout 3- 35 avss 34 dvss 12 sdti 1 13 sdti 2 14 sdti 3 15 lrck 16 smute 17 cclk 18 cdti 19 csn 20 dfs 0 21 cks 0 22 33 32 31 30 29 28 27 26 25 24 23 avdd vrefh dzfr2 dzfl3 dzfr3 dzfe dif2 dif1 dif0 cks2 cks1 AK4356vq top view
asahi kasei [AK4356] m0072-e-01 1999/09 - 4 - pin/function no. pin name i/o function 1 lout1- o dac1 lch negative analog output pin 2 lout1+ o dac1 lch positive analog output pin 3 dzfl2 o dac2 lch zero input detect pin 4 dzfr1 o dac1 rch zero input detect pin 5 dzfl1 o dac1 lch zero input detect pin 6 cad0 i chip address 0 pin 7 cad1 i chip address 1 pin 8 pdn i power-down & reset pin when l, the AK4356 is powered-down and the control registers are reset to default state. if the state of cad0-1 changes, then the AK4356 must be reset by pdn. 9 bick i audio serial data clock pin 10 mclk i master clock input pin 11 dvdd - digital power supply pin, +4.75 ~ +5.25v 12 dvss - digital ground pin 13 sdti1 i dac1 audio serial data input pin 14 sdti2 i dac2 audio serial data input pin 15 sdti3 i dac3 audio serial data input pin 16 lrck i audio input channel clock pin 17 smute i soft mute pin (note) when this pin goes to h, soft mute cycle is initialized. when returning to l, the output mute releases. 18 cclk i control data clock pin 19 cdti i control data input pin 20 csn i chip select pin this pin should be held to h except for access.
asahi kasei [AK4356] m0072-e-01 1999/09 - 5 - no. pin name i/o function 21 dfs0 i double speed sampling mode 0 pin (note) l: normal speed, h: double speed at dfs1 bit = 0. 22 cks0 i input clock select 0 pin (note) 23 cks1 i input clock select 1 pin (note) 24 cks2 i input clock select 2 pin (note) 25 dif0 i audio data interface format 0 pin (note) 26 dif1 i audio data interface format 1 pin (note) 27 dif2 i audio data interface format 2 pin (note) 28 dzfe i zero input detect enable pin (note) 29 dzfr3 o dac3 rch zero input detect pin 30 dzfl3 o dac3 lch zero input detect pin 31 dzfr2 o dac2 rch zero input detect pin 32 vrefh i positive voltage reference input pin, avdd 33 avdd - analog power supply pin 34 avss - analog ground pin, +4.75 ~ +5.25v 35 rout3- o dac3 rch negative analog output pin 36 rout3+ o dac3 rch positive analog output pin 37 lout3- o dac3 lch negative analog output pin 38 lout3+ o dac3 lch positive analog output pin 39 rout2- o dac2 rch negative analog output pin 40 rout2+ o dac2 rch positive analog output pin 41 lout2- o dac2 lch negative analog output pin 42 lout2+ o dac2 lch positive analog output pin 43 rout1- o dac1 rch negative analog output pin 44 rout1+ o dac1 rch positive analog output pin note:smute, dfs0, cks0, cks1, cks2, dif0, dif1, dif2, dzfe pins are ored with serial control register.
asahi kasei [AK4356] m0072-e-01 1999/09 - 6 - absolute maximum ratings (avss, dvss=0v; note 1) parameter symbol min max units power supplies analog digital |avss-dvss| (note 2) avdd dvdd d gnd -0.3 -0.3 - 6.0 6.0 0.3 v v v input current (any pins except for supplies) iin - 10 ma analog input voltage vina -0.3 avdd+0.3 v digital input voltage vind -0.3 dvdd+0.3 v ambient temperature ta -40 85 c storage temperature tstg -65 150 c note:1. all voltages with respect to ground. 2. avss and dvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss=0v; note 1) parameter symbol min typ max units power supplies (note 3) analog digital avdd dvdd 4.75 4.75 5.0 5.0 5.25 5.25 v v note:1. all voltages with respect to ground. 3. the power up sequence between avdd and dvdd is not critical. *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [AK4356] m0072-e-01 1999/09 - 7 - analog characteristics (ta=25 c; avdd, dvdd=5v; avss, dvss=0v; vrefh=avdd; fs=44.1khz; bick=64fs; signal frequency =1khz; 24bit data; r l 3 2k w ; measurement frequency=20hz ~ 20khz at 44.1khz, 20hz~40khz at fs=96khz, 20hz~80khz at fs=192khz; unless otherwise specified) parameter min typ max units dynamic characteristics (note 4) resolution 24 bits s/(n+d) fs=44.1khz fs=96khz 88 86 94 92 db db dr (-60dbfs) fs=44.1khz, a-weighted fs=96khz 106 - 112 105 db db s/n (note 5,6) fs=44.1khz, a-weighted fs=96khz 106 - 112 105 db db interchannel isolation 90 110 db dc accuracy interchannel gain mismatch 0.2 0.5 db gain drift (note 7) 20 - ppm/ c output voltage (aout+) - (aout-) (note 8) 2.55 2.75 2.95 vpp load resistance (note 9) 2 k w load capacitance 25 pf power supply rejection (note 10) 50 db power supplies power supply current normal operation (pdn = h) avdd dvdd (fs=44.1khz) (fs=96khz) (fs=192khz) power-down-mode (pdn = l) avdd+dvdd (note 11) 60 15 20 15 10 90 30 40 30 100 ma ma ma ma m a note: 4. measured by upd(rohde & schwarz). refer to the evaluation board manual. 5. 107db at ccir-arm weighted 6. s/n is independent of input bit length. 7. vrefh is constantly +5.0v. 8. full scale voltage (0db). output voltage scales with the voltage of vrefh pin. aout(typ.@0db)=(aout+)-(aout-)= 2.75vpp*vrefh/5.0 9. ac load 10. psr is applied to avdd, dvdd with 1khz, 100mvpp. vrefh pin is held a constant voltage. 11. all digital input pins including clock pins (mclk, bick and lrck) are connected to dvss.
asahi kasei [AK4356] m0072-e-01 1999/09 - 8 - filter characteristics (fs=44.1khz) (ta=25 c; avdd, dvdd=4.75 ~ 5.25v; fs=44.1khz; dfs1 = dfs0 = 0; dem=off) parameter symbol min typ max units digital filter passband (note 12) 0.01db -6.0db pb 0 - 22.05 20.0 - khz khz stopband (note 12) sb 24.1 khz passband ripple pr 0.005 db stopband attenuation sa 75 db group delay (note 13) gd - 27.2 - 1/fs digital filter + scf frequency response: 0 ~ 20.0khz fr - 0.2 -db note:12. the passband and stopband frequencies scale with fs. for example, pb=0.4535*fs(@0.01db), sb=0.546*fs. 13. the calculating delay time which occurred by digital filtering. this time is from setting the 16/20/24bit data of both channels on the input register to the output of analog signal. filter characteristics (fs=96khz) (ta=25 c; avdd, dvdd=4.75 ~ 5.25v; fs=96khz; dfs1 = 0; dfs0 = 1; dem=off) parameter symbol min typ max units digital filter passband (note 14) 0.01db -6.0db pb 0 - 48.0 43.5 - khz khz stopband (note 14) sb 52.5 khz passband ripple pr 0.005 db stopband attenuation sa 75 db group delay (note 13) gd - 27.2 - 1/fs digital filter + scf frequency response: 0 ~ 40.0khz fr - 0.3 -db note:14. the passband and stopband frequencies scale with fs. for example, pb=0.4535*fs(@0.01db), sb=0.546*fs.
asahi kasei [AK4356] m0072-e-01 1999/09 - 9 - filter characteristics (fs=192khz) (ta=25 c; avdd, dvdd=4.75 ~ 5.25v; fs=192khz; dfs1 = 1; dfs0 = 0; dem=off) parameter symbol min typ max units digital filter passband (note 15) 0.01db -6.0db pb 0 - 96.0 87.0 - khz khz stopband (note 15) sb 105 khz passband ripple pr 0.005 db stopband attenuation sa 75 db group delay (note 13) gd - 27.2 - 1/fs digital filter + scf frequency response: 0 ~ 80.0khz fr - 0.5 -db note:15. the passband and stopband frequencies scale with fs. for example, pb=0.4535*fs(@0.01db), sb=0.546*fs. digital characteristics (ta=25 c; avdd, dvdd=4.75 ~ 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v hight-level output voltage (iout= -100 m a) low-level output voltage (iout= 100 m a) voh vol dvdd-0.5 - - - - 0.5 v v input leakage current iin - - 10 m a
asahi kasei [AK4356] m0072-e-01 1999/09 - 10 - switching characteristics (ta=25 c; avdd, dvdd=4.75 ~ 5.25v; c l =20pf) parameter symbol min typ max units master clock timing frequency duty fclk duty 8.192 40 36.864 60 mhz % lrck frequency (note 16) normal speed mode (dfs1-0 = 00) double speed mode (dfs1-0 = 01) 4 times speed mode (dfs1-0 = 10) duty cycle fsn fsd fsq duty 32 64 128 45 48 96 192 55 khz khz khz % serial interface timing bick period normal speed mode double speed mode 4 times speed mode bick pulse width low pulse width high bick - to lrck edge (note 17) lrck edge to bick - (note 17) sdti hold time sdti setup time tbck tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fs 1/64fs 1/64fs 33 33 20 20 20 20 ns ns ns ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn h time csn to cclk - cclk - to csn - rise time of csn fall time of csn rise time of cclk fall time of cclk tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tr1 tf1 tr2 tf2 200 80 80 40 40 150 50 50 20 20 20 20 ns ns ns ns ns ns ns ns ns ns ns ns power-down/reset timing pdn pulse width (note 18) tpdw 150 ns note:16. if sampling speed mode (dfs0-1) changes, please reset by pdn pin or rstn bit. 17. bick rising edge must not occur at the same time as lrck edge. 18. the AK4356 can be reset by pdn pin l upon power up. if cks0-2 or dfs0-1 changes, the AK4356 should be reset by pdn pin or rstn bit.
asahi kasei [AK4356] m0072-e-01 1999/09 - 11 - n timing diagram vih mclk vil tclk vih lrck vil 1/fs tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr audio interface timing
asahi kasei [AK4356] m0072-e-01 1999/09 - 12 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing tpdw vil pdn power-down & reset timing
asahi kasei [AK4356] m0072-e-01 1999/09 - 13 - operation overview n system clock input the external clocks which are required to operate the AK4356 are mclk, lrck and bick. the master clock (mclk) should be synchronized with sampling clock (lrck) but the phase is not critical. mclk is used to operate the digital interpolation filter and the delta-sigma modulator. the frequency of mclk can be set by cks0-2, and can be selected to normal, double or 4 times speed mode by dfs0-1 (see table 1). 4 times speed mode can be used for only dac1. if dac1 is in 4 times speed mode, dac2 and dac3 are automatically powered down. when the states of slow, dif2-0, dfs1-0 or cks2-0 changes, the AK4356 should be reset by pdn pin or rstn bit. all external clocks (mclk, bick and lrck) should always be present whenever the AK4356 is in normal operation mode (pdn = h). if these clocks are not provided, the AK4356 may draw excess current and may not possibly operate properly because the device utilizes dynamic refreshed logic internally. if the external clocks are not present, the AK4356 should be in the power-down mode (pdn = l or all dacs are set in the power-down mode by pw1-3 bits) or in the reset mode (rstn = 0). after exiting reset at power-up etc., the AK4356 is in the power-down mode until mclk and lrck are input. dfs1-0 mode cks2 cks1 cks0 00 (normal speed) 01 (double speed) 10 (4 times speed) 000 0 256fs 128fs n/a default (dfs1-0 = 00) 1 0 0 1 256fs 256fs n/a 2 0 1 0 384fs 192fs n/a 3 0 1 1 384fs 384fs n/a 4 1 0 0 512fs 256fs 128fs 5 1 0 1 512fs n/a n/a 6 1 1 0 768fs 384fs 192fs 7 1 1 1 768fs n/a n/a table 1. system clock (dfs1-0 = 11: reserved) fs [khz] mode 128fs 192fs 256fs 384fs 512fs 768fs 32 64 128 normal double 4 times - 8.1920 16.3840 - 12.2880 24.5760 8.1920 16.3840 - 12.2880 24.5760 - 16.3840 - - 24.5760 - - 44.1 88.2 176.4 normal double 4 times - 11.2896 22.5792 - 16.9344 33.8688 11.2896 22.5792 - 16.9344 33.8688 - 22.5792 - - 33.8688 - - 48 96 192 normal double 4 times - 12.2880 24.5760 - 18.4320 36.8640 12.2880 24.5760 - 18.4320 36.8640 - 24.5760 - - 36.8640 - - table 2. example of system clock [mhz]
asahi kasei [AK4356] m0072-e-01 1999/09 - 14 - n audio serial interface format audio data is input to the AK4356 via the sdti1-3 pins using bick and lrck inputs. 5 serial data formats are supported and selected by dif2-0 pins or dif2-0 bits (see table 3, compatible with the ak4324/4393). in all modes the serial data is msb-first, 2s compliment format and is latched on the rising edge of bick. mode 2 can be used for 20 and 16 msb justified formats by zeroing the unused lsbs. mode dif2 dif1 dif0 sdti l/r bick figure 0 0 0 0 16bit, lsb justified h/l 3 32fs figure 1 default 1 0 0 1 20bit, lsb justified h/l 3 40fs figure 2 2 0 1 0 24bit, msb justified h/l 3 48fs figure 3 3011 i2s l/h 32fs or 3 48fs figure 4 4 1 0 0 24bit, lsb justified h/l 3 48fs figure 2 table 3. audio data format sdti bick lrck sdti 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3210 1514 ( 32fs ) ( 64fs ) 014 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 dont care dont care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 1. mode 0 timing
asahi kasei [AK4356] m0072-e-01 1999/09 - 15 - sdti lrck bick ( 64fs ) 09 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 dont care dont care 19:msb, 0:lsb sdti mode 4 23:msb, 0:lsb 20 19 0 20 19 0 dont care dont care 22 21 22 21 lch data rch data 8 23 23 8 figure 2. mode 1,4 timing lrck bick ( 64fs ) sdti 022 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 dont care 23 lch data rch data 23 30 22 224 23 30 22 1 0 dont care 23 22 23 figure 3. mode 2 timing
asahi kasei [AK4356] m0072-e-01 1999/09 - 16 - lrck bick ( 64fs ) sdti 03 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 dont care 23 lch data rch data 23 25 3 224 23 25 22 1 0 dont care 23 bick ( 32fs ) sdti 03 1 2 12 15 0 1 0 1 23 22 13 8 11 14 2 12 11 10 9 13 3 12 15 11 14 13 23 22 13 8 12 11 10 9 23 8 23 figure 4. mode 3 timing n n n n output volume the AK4356 includes channel independent digital output volumes (att) with 256 levels at 0.5db steps including mute. these volumes are in front of the dac and can attenuate the input data from 0db to C127db and mute. when changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. n n n n de-emphasis filter a digital de-emphasis filter is available for 32, 44.1 or 48khz sampling rates (tc=50/15 m s). it can be set for dac1 (sdti1), dac2 (sdti2) and dac3 (sdti3) independently. it is enabled or disabled with the control register data of dem1-0 and dfs1-0. the de-emphasis filter is disabled at double or 4 times sampling mode (except for dfs0 = dfs1 = 0). dem1 dem0 de-emphasis 0 0 44.1khz 0 1 off default 1 0 48khz 1 1 32khz table 4. de-emphasis filter control with dem1-0 (dfs1-0 = 00) dfs1 dfs0 de-emphasis 0 0 see table 4. default 01 off 10 off 11 off table 5. de-emphasis filter control with dfs1-0
asahi kasei [AK4356] m0072-e-01 1999/09 - 17 - n zero detection the AK4356 has channel-independent zeros detect function. when the input data at each channel is continuously zero for 8192 lrck cycles, dzf pin of each channel goes to h. dzf pin of each channel immediately goes to l if input data of each channel is not zero after going dzf h. if rstn bit is 0, dzf pins of all channels go to h. dzf pins of all channels go to l 4/fs after rstn bit returns to 1. if dzfm bit is set to 1, dzf pins of all channels go to h only when the input data at all channels are continuously zeros for 8192 lrck cycles. zero detect function can be disabled by dzfe bit. in this case, dzf pins of all channels are always l (except for the case of rstn = 0). n soft mute operation soft mute operation is performed at digital domain. when the smute pin goes to h, the output signal is attenuated by - during 1024 lrck cycles. when the smute pin is returned to l, the mute is cancelled and the output attenuation gradually changes to 0db during 1024 lrck cycles. if the soft mute is cancelled within 1024 lrck cycles after starting the operation, the attenuation is discontinued and returned to 0db. the soft mute is effective for changing the signal source without stopping the signal transmission. smute attenuation dzf 1024/fs 0db - aout 1024/fs 8192/fs gd gd (1) (2) (3) (4) notes: (1) the output signal is attenuated by - during 1024 lrck cycles (1024/fs). (2) analog output corresponding to digital input have the group delay (gd). (3) if the soft mute is cancelled within 1024 lrck cycles, the attenuation is discontinued and returned to 0db. (4) when the input data at each channel is continuously zeros for 8192 lrck cycles, dzf pin of each channel goes to h. dzf pin immediately goes to l if input data are not zero after going dzf h. figure 5. soft mute and zero detection n system reset the AK4356 should be reset once by bringing pdn = l upon power-up. the AK4356 is powered up and the internal timing starts clocking by lrck - after exiting reset and power down state by mclk. the AK4356 is in the power-down mode until mclk and lrck are input.
asahi kasei [AK4356] m0072-e-01 1999/09 - 18 - n power-down all dacs are placed in the power-down mode by bringing pdn pin l and each digital filter is also reset at the same time. the internal register values are initialized by pdn l. this reset should always be done after power-up. because some click noise occurs at the edge of pdn, the analog output should be muted externally if the click noise influences system application. figure 6 shows the power-down/up sequence. each dac can be powered down by each power-down bit (pw1-3) 0. in this case, the internal register values are not initialized and the analog output is hi-z. because some click noise occurs, the analog output should be muted externally if the click noise influences system application. if dac1 is in 4 times speed mode (dfs1=1, dfs0=0), dac2 and dac3 are automatically powered down. both analog outputs go to analog common voltage (avdd/2). normal operation internal state pdn power-down normal operation gd gd 0 data d/a out (analog) d/a in (digital) clock in mclk, lrck, bick (1) (3) (6) dzf external mute (5) (3) (1) mute on (2) (4) dont care notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs are floating (hi -z) at the power-down mode. (3) click noise occurs at the edge of pdn signal. this noise is output even if 0 data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the power-down mode (pdn = l). (5) please mute the analog output externally if the click noise (3) influences system application. the timing example is shown in this figure. (6) dzf pins of all channels are l in the power-down mode (pdn = l). figure 6. power-down/up sequence example
asahi kasei [AK4356] m0072-e-01 1999/09 - 19 - n reset function when rstn=0, all dacs are powered down but the internal register values are not initialized. the analog outputs go to vcom voltage and dzf pins of all channels go to h. figure 7 shows the sequence of reset by rstn bit. internal state rstn bit digital block power-down normal operation gd gd 0 data d/a out (analog) d/a in (digital) clock in mclk,lrck,bick (1) (3) dzfl/dzfr (3) (1) (2) normal operation 2/fs(5) internal rstn bit 2~3/fs (6) dont care (4) notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs go to vcom voltage. (3) click noise occurs at the edges( - ) of the internal timing of rstn bit. this noise is output even if 0 data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the reset mode (rstn = l). (5) dzf pins go to h when the rstn bit becomes 0, and go to l at 4~5/fs after rstn bit becomes 1. (6) there is a delay, 2~3/fs from rstn bit 1 to the internal rstn 1. figure 7. reset sequence example
asahi kasei [AK4356] m0072-e-01 1999/09 - 20 - n serial control interface the AK4356 can control its functions via both pins and registers. cks2-0, dif2-0, dfs0, dzfe and smute pins are ored with their registers. internal registers may be written to the 3 wire up interface pins: csn, cclk & cdti. the data on this interface consists of chip address (2bits, cad0/1), read/write (1bit), register address (msb first, 5bits) and control data (msb first, 8bits). address and data is clocked in on the rising edge of cclk. data is latched after a low-to-high transition of csn. the clock speed of cclk is 5mhz(max). the csn pin should be held to h except for access. the chip address is determined by the state of the cad0 and cad1 inputs. pdn = l initializes the registers to their default values. writing 0 to the rstn bit can initialize the internal timing circuit. but in this case, the register data is not be initialized. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (c1=cad1, c0=cad0) r/w: read/write (fixed to 1 : write only) a4-a0: register address d7-d0: control data figure 7. control i/f timing function pin set-up register set-up double speed o o 4 times speed x o de-emphasis x o dzfe o o dzfm x o smute o o attenuator x o slow roll-off response x o table 6. function table (o: supported, x: not supported) note: writing to control register is inhibited when pdn = l or the mclk is not fed.
asahi kasei [AK4356] m0072-e-01 1999/09 - 21 - n mapping of program registers addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 slow dzfm dzfe dif2 dif1 dif0 rstn 01h control 2 0 0 0 cks2 cks1 cks0 smute rstn 02h speed & power down control 0 0 dfs1 dfs0 pw3 pw2 pw1 rstn 03h de-emphasis control 0 0 demc1 demc0 demb1 demb0 dema1 dema0 04h lout1 att control att7 att6 att5 att4 att3 att2 att1 att0 05h rout1 att control att7 att6 att5 att4 att3 att2 att1 att0 06h lout2 att control att7 att6 att5 att4 att3 att2 att1 att0 07h rout2 att control att7 att6 att5 att4 att3 att2 att1 att0 08h lout3 att control att7 att6 att5 att4 att3 att2 att1 att0 09h rout3 att control att7 att6 att5 att4 att3 att2 att1 att0 0ah test mode 0 0 0 test4 test3 test2 test1 test0 note: for addresses from 0bh to 1fh, data is not written. when pdn goes to l, the registers are initialized to their default values. when rstn bit goes to 0, the internal timing is reset, dzf pins of all channels go to h but registers are not initialized to their default values. dzfe, dif2-0, cks2-0, smute and dfs0 are ored with pins.
asahi kasei [AK4356] m0072-e-01 1999/09 - 22 - n register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 slow dzfm dzfe dif2 dif1 dif0 rstn default 00000001 rstn: internal timing reset 0: reset. dzf pins of all channels go to h and registers are not initialized. 1: normal operation when the states of slow, dif2-0, cks2-0 or dfs0-1 changes, the AK4356 should be reset by pdn pin or rstn bit. some click noise occurs at that timing. dif2-0: audio data interface modes (see table 3.) initial: 000, mode 0 register bits of dif2-0 are ored with the dfs2-0 pins. dzfe: data zero detect enable 0: disable 1: enable zero detect function can be disabled by dzfe bit. in this case, the dzf pins of all channels are always l. register bit of dzfe is ored with the dzfe pin. dzfm: data zero detect mode 0: channel separated mode 1: channel anded mode if the dzfm bit is set to 1, the dzf pins of all channels go to h only when the input data at all channels are continuously zeros for 8192 lrck cycles. slow: slow roll-off response enable 0: disable 1: enable addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 0 0 0 cks2 cks1 cks0 smute rstn default 00000001 rstn: internal timing reset 0: reset. dzf pins of all channels go to h and registers are not initialized. 1: normal operation when the states of slow, dif2-0, cks2-0 or dfs0-1 changes, the AK4356 should be reset by pdn pin or rstn bit. some click noise occurs at that timing. smute: soft mute enable 0: normal operation 1: all dac outputs soft-muted register bit of smute is ored with the smute pin. cks2-0: master clock frequency select (see table 2.) initial: 000, mode 0 register bits of cks2-0 are ored with the cks2-0 pins.
asahi kasei [AK4356] m0072-e-01 1999/09 - 23 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h speed & power down control 0 0 dfs1 dfs0 pw3 pw2 pw1 rstn default 00001111 rstn: internal timing reset 0: reset. dzf pins of all channels go to h and registers are not initialized. 1: normal operation when the states of slow, dif2-0, cks2-0 or dfs0-1 changes, the AK4356 should be reset by pdn pin or rstn bit. some click noise occurs at that timing. pw3-1: power-down control (0: power-down, 1: power-up) pw1: power down control of dac1 pw2: power down control of dac2 pw3: power down control of dac3 all sections are powered-down by pw1=pw2=pw3=0. dfs1-0: sampling speed control (see table 1.) 00: normal speed 01: double speed 10: 4 times speed (dac2 and dac3 are automatically powered down.) register bit of dfs0 is ored with the dfs0 pin. when sampling speed mode is changed between normal and double/4 times speed mode, dfs1-0 bit should be changed after changing mclk frequency (figure below). some click noise occurs at this timing. sampling speed mclk normal 4 times /double normal when sampling speed mode is changed between double and 4 times speed mode, sampling mode should be changed to normal speed mode after changing mclk frequency, and then it should be changed to double/4 times speed mode (figure below). some click noise occurs at those changing timing. sampling speed mclk double/ 4 times normal 4 times /double addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h de-emphasis control 0 0 demc1 demc0 demb1 demb0 dema1 dema0 default 00010101 dema1-0: de-emphasis response control for dac1 data on sdti1 (see table 4,5.) initial: 01, off demb1-0: de-emphasis response control for dac2 data on sdti2 (see table 4,5.) initial: 01, off demc1-0: de-emphasis response control for dac3 data on sdti3 (see table 4,5.) initial: 01, off
asahi kasei [AK4356] m0072-e-01 1999/09 - 24 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h lout1 att control att7 att6 att5 att4 att3 att2 att1 att0 05h rout1 att control att7 att6 att5 att4 att3 att2 att1 att0 06h lout2 att control att7 att6 att5 att4 att3 att2 att1 att0 07h rout2 att control att7 att6 att5 att4 att3 att2 att1 att0 08h lout3 att control att7 att6 att5 att4 att3 att2 att1 att0 09h rout3 att control att7 att6 att5 att4 att3 att2 att1 att0 default 11111111 att7-0: attenuation level 256 levels, 0.5db step att7-0 attenuation ffh 0db feh -0.5db fdh -1.0db : : : : 02h -126.5db 01h -127.0db 00h mute (- ) the transition between set values is soft transition of 7425 levels. it takes 7424/fs (168ms@fs=44.1khz) from ffh(0db) to 00h(mute). if pdn pin goes to l, the atts are initialized to ffh. the atts are ffh when rstn = 0. when rstn return to 1, the atts fade to their current value. digital attenuator is independent of soft mute function. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah test mode 0 0 0 test4 test3 test2 test1 test0 default 00000000 test4-0: test mode
asahi kasei [AK4356] m0072-e-01 1999/09 - 25 - system design figure 8 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. condition: chip address=00 dvss dvdd 12 sdti1 11 13 sdti2 14 sdti3 15 lrck 16 smute 17 cclk 18 cdti 19 csn 20 dfs0 21 cks0 22 mclk 10 bick 9 pdn 8 cad1 7 cad0 6 dzfl1 5 dzfr 1 4 dzfl2 3 lout1+ 2 lout 1 - 1 cks1 23 cks 2 24 dif0 2 5 dif 1 26 dif2 2 7 dzfe 28 dzfr3 29 dzfl 3 30 dzfr2 31 vrefh 32 avdd 33 44 43 42 41 40 39 38 37 36 35 34 rout1+ rout1- lout2+ lout2- rout2+ rout2- lout3+ lout3- rout3+ rout3- avss AK4356 top view dir dsp up + mode control r3ch lpf l3ch lpf r2ch lpf l2ch lpf r1ch lpf l1ch lpf l1ch mute l1ch out r1ch mute r1ch out l2ch mute l2ch out r2ch mute r2ch out l3ch mute l3ch out r3ch mute r3ch out + analog 5v digital 5v system ground analog ground reset 10u 0.1u 0.1u 10u figure 8. typical connection diagram
asahi kasei [AK4356] m0072-e-01 1999/09 - 26 - analog ground digital ground system controller dvss dvdd 12 sdti1 11 13 sdti2 14 sdti3 15 lrck 16 smute 17 cclk 18 cdti 19 csn 20 dfs0 21 cks0 22 cks1 23 44 rout1+ AK4356 24 25 26 27 28 29 30 31 32 33 cks2 dif0 dif1 dif2 dzfe dzfr3 dzfl3 dzfr2 vrefh avdd 43 rout1- 42 lout2+ 41 lout2- 40 rout2+ 39 rout2- 38 lout3+ 37 lout3- 36 rout3+ 35 rout3- 34 avss mclk 10 bick 9 pdn 8 cad1 7 cad0 6 dzfl1 5 dzfr1 4 dzfl2 3 lout1+ 2 lout1- 1 figure 9. ground layout note: avss and dvss must be connected to the same analog ground plane. 1. grounding and power supply decoupling the AK4356 requires careful attention to power supply and grounding arrangements. avdd and dvdd are usually supplied from analog supply in system. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical. avss and dvss of the AK4356 must be connected to analog ground plane . system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be near to the AK4356 as possible, with the small value ceramic capacitors being the nearest. 2. voltage reference inputs vrefh sets the analog output range. vrefh pin is normally connected to avdd with a 0.1 m f ceramic capacitor. all signals, especially clocks, should be kept away from the vrefh pin in order to avoid unwanted coupling into the AK4356. 3. analog outputs the analog outputs are full-differential outputs and 0.55 x vrefh vpp (typ) centered around the internal common voltage (about avdd/2). the differential outputs are summed externally, v aout =(aout+)-(aout-) between aout+ and aout-. if the summing gain is 1, the output range is 5.5vpp (typ @vrefh=5v). the bias voltage of the external summing circuit is supplied externally. the input data format is 2s complement. the output voltage(v aout ) is a positive full scale for 7fffff(@24bit) and a negative full scale for 800000h(@24bit). the ideal v aout is 0v for 000000h(@24bit). the internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. dc offset on aout+/- is eliminated without ac coupling since the analog outputs are differential. figure 10 and 11 show the example of external op-amp circuit summing the differential outputs.
asahi kasei [AK4356] m0072-e-01 1999/09 - 27 - 4.7k 4.7k r1 4.7k r1 4.7k 470p vop 470p vop 1k 1k 47u 0.1u bias aout- aout+ 3300p when r1=200 w when r1=180 w fc=93.2khz, q=0.712, g=-0.1db at 40khz fc=98.2khz, q=0.681, g=-0.2db at 40khz analog out figure 10. external 2 nd order lpf circuit example (using op-amp with single power supply) 4.7k 4.7k r1 4.7k r1 4.7k 470p +vop 470p -vop aout- aout+ 3300p when r1=200 w when r1=180 w fc=93.2khz, q=0.712, g=-0.1db at 40khz fc=98.2khz, q=0.681, g=-0.2db at 40khz analog out figure 11. external 2 nd order lpf circuit example (using op-amp with dual power supplies)
asahi kasei [AK4356] m0072-e-01 1999/09 - 28 - package 0.15 0.17 0.05 0.37 0.10 10.00 1.70max 111 23 33 44pin lqfp ( unit: mm ) 10.00 12.80 0.30 34 44 0.80 22 12 12.80 0.30 0 ~ 0.2 0 ~ 10 0.60 0.20 n package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
asahi kasei [AK4356] m0072-e-01 1999/09 - 29 - marking akm AK4356vq xxxxxxx japan 1 1) pin #1 indication 2) date code: xxxxxxx(7 digits) 3) marking code: AK4356vq 4) country of origin 5) asahi kasei logo important notice these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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